Arrays of analog/digital converters operating in parallel comprise a plurality of analog/digital converters which digitize an analog signal in parallel but with a certain timing offset. The individual digital signals are then recombined using a multiplexer, so that effectively a higher sampling rate than that of the individual analog/digital converters is achieved. Such converter arrays are also called TIADCs (Time Interleaved Analog to Digital Converters).
In the simplest case of a TIADC, two analog/digital converters are connected in parallel, alternately sample a common analog input signal and digitize it. As a result, the sampling or conversion rate of the overall system appears to be twice that of the sampling rate of the individual analog/digital converters.
In the more general case, increasing the number of analog/digital converters operating in parallel or increasing the number of channels, in the case of N analog/digital converters, allows the effective sampling rate of the converter array to be increased to N times the sampling rate of a single analog/digital converter.
FIG. 1 shows a converter array or TIADC based on the prior art. There are N analog/digital converters A/D1, A/D2, . . . , A/DN, which each have an analog input E1, E2, . . . , EN, a digital output A1, A2, . . . , AN and an input C1, C2, . . . , CN for a respective clock signal CLK1, CLK2, . . . , CLKN.
The analog inputs E1, E2, . . . , EN have a common analog input signal VIN applied to them. The outputs A1, A2, . . . , AN of the analog/digital converters A/D1, A/D2, . . . , A/DN deliver respective digital intermediate signals Z1, Z2, . . . , ZN which are switched through in succession by a downstream multiplexer MUX as digital output signal ZD from the TIADC.
A clock generator CLKG produces a global clock signal CLK, which is routed to a delay locked loop DLL and is used to produce an N phase clock, or N clock signals CLK1, CLK2, . . . , CLKN which each have the same clock period T as the global clock signal CLK, but in each case with a delay by a timing offset of T/N=ΔT. These clock signals CLK1, CLK2, . . . , CLKN are each routed to the clock inputs C1, C2, . . . , CN of the individual analog/digital converters A/D1, A/D2, . . . , A/DN.
In the case of such arrays, there is the difficulty that any type of inequality among the individual converters results in conversion errors. By way of example, different offset values in the various analog/digital converters result in interfering sounds at frequencies which comprise whole portions of the sampling frequency. Different nonlinearities in the channels, differences in the gain, discrepancies from the ideal sampling time or a different bandwidth in the analog/digital converters also result in unwanted interference in the digital output signal.
In particular, different nonlinearity properties in the analog/digital converters used result in output signal energies in the converter array's frequency spectrum which interfere.
FIG. 2 shows the characteristic for a 3-bit analog/digital converter by way of example. In the case of a characteristic or transfer function for an analog/digital converter, the digital output signal Z is plotted over the analog input signal VIN, which in this case has been normalized to the maximum level of the analog input signal VINMAX. An ideal converter with infinitely high resolution would result in an exact bisector IAD as characteristic. An ideal characteristic for an ideal analog/digital converter with finite resolution provides a staircase curve I3BAD, the steps all having the same width and height. The dotted line corresponds to a characteristic for a 3-bit analog/digital converter which has two nonlinearities NL1, NL2. The integral nonlinearity or the linearity error is a measure of the maximum discrepancy in the converter characteristic from the bisector and is normally indicated in the number of the least significant bit. The nonlinearity NL1 is a positive linearity error, for example, and the nonlinearity NL2 is a negative nonlinearity error.
Methods are known for reducing but not eliminating nonlinearities in analog/digital converters. FIG. 3A shows a basic circuit diagram of a flash analog/digital converter by way of example.
The converter has a plurality of comparators K1–K8 which each have a first input EF1–EF8, a second input DF1–DF8 and an output AF1–AF8. The first inputs EF1–EF8 have received an analog input signal VIN.
A resistor ladder is provided which comprises a plurality of resistors R1–R8 which are connected between a first reference voltage VREF and a second reference voltage or ground GND. Between the resistors, it is possible to tap off reference potentials U0–U7 which are each routed to the second inputs DF1–DF8 of the comparators K1–K8.
The comparators K1–K8 deliver intermediate signals W1–W8 which are routed to a decoder DEK. Since the comparators K1–K8 have different switching potentials or switching thresholds as a result of the reference voltage U0–U7, the intermediate signals W1–W8 map the analog input signal into a digital signal in the thermometer code. This thermometer code is converted into a suitable digital code by the decoder DEK and is output as a digital output signal WD.
A corresponding analog/digital converter such as is shown in FIG. 3A normally has nonlinearities as a result of comparators K1–K8 which are not of exactly identical design. This may be caused inter alia, by fluctuations in the substrate properties of a semiconductor substrate on which the converter is produced. As a result, the switching thresholds of the comparators may not be exactly equidistant, for example, and hence may cause one or more nonlinearities in the transfer characteristic of the converter.
FIG. 3B describes a possible compensation for nonlinearities by virtue of topological interchange of the resistors in the resistor ladders.
Accordingly, the resistors in the resistor ladders are connected up such that the voltage dropping across the original resistor R1 or the corresponding reference potential U1 is routed to the comparator K2.
The voltage U2 dropping across the original resistor R8 (in this case referred to as R2′) is connected to the third comparator K3.
The voltage U3 dropping across the original resistor R2 (in this case referred to as R3′) is connected to the fourth comparator K4.
The voltage U5 dropping across the original resistor R7 (in this case referred to as R4′) is connected to the comparator K5.
The voltage U6 dropping across the original resistor R6 (in this case referred to as R6′) is connected to the comparator K7.
Finally, the voltage U7 dropping across the original resistor R4 (in this case referred to as R7′) is connected to the comparator K8.
Hence, the resistor R1 from FIG. 3B corresponds to the resistor R1 from FIG. 3A, the resistor R3′ corresponds to the resistor R2, the resistor R4′ corresponds to the resistor R7, the resistor R5′ corresponds to the resistor R3, the resistor R6′ corresponds to the resistor R6, the resistor R7′ corresponds to the resistor R4, and the resistor R8′ corresponds to the resistor R5.
Such topological interchange based on the prior art in order to compensate for or reduce nonlinearities is very complex in terms of connections, however. This additional connection also causes parasitic capacitance which severely restricts the maximum clock frequency of the flash converter. Furthermore, such additional connection needs to be reserved for each analog/digital converter contained in a converter array as described in FIG. 1. The method of topological interchange is therefore disadvantageous for analog/digital converters which are provided for use in TIADCs or converter arrays.
It is therefore an object of the present invention to provide a circuit arrangement for compensating for nonlinearities from analog/digital converters operating with different timing which has low circuit complexity and can be implemented independently of production technology.